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VLSI Training in Bangalore
 
Syllabus Overview - IIVDT PGDVDT

Post-Graduate Diploma in VLSI Design Technology is an intensive and highly modular course with each module provides comprehensive training on specific aspect of the VLSI Design flow. Each module contains thorough case study or tutorial to convert knowledge into learning. After each module students have to appear and clear online test to continue further in the stream.

Beside the tutorials and online examinations, student's learning is also evaluated through group project taken during the course. Due to world class course content and rigorous evaluation criterions, PGDVDT lifts the knowledge of the students in VLSI Design domain to the professional level. This proficiency in VLSI Design flow enables students to get easily absorbed in VLSI industry.

Overview of Post-Graduate Diploma in VLSI Design Technology

SoC Design Training India
 

Front End VLSI Design Training Flow

Architecture

SoC Bus Structure - AHB, APB, AXI
SoC Design Training Institute SoC Processor Architecture
Institute For ASIC Training SoC Peripherals
Area Optimization
SoC Design Training Institute Frequency Optimization
Institute For ASIC Training SoC Architecture Tutorial

Logic Design

FSM Design & FIFO Design
SoC Design Training Institute Verilog Coding
Institute For ASIC Training Handshaking Protocols
Math Function Implementations
SoC Design Training Institute Reset Design
Institute For ASIC Training Clock Management

Advanced Verification

Testbench Architecture
SoC Design Training Institute System Verilog & Assertions
Institute For ASIC Training Verification Methodologies
Coverage Methods
SoC Design Training Institute GLS Verification & Debugging Tips
Institute For ASIC Training Verification Tutorial

ASIC Design Training
 

ASIC Netlist Generation Flow

RTL Synthesis

Synthesis Strategies
SoC Design Training Institute Synthesis Scripts
Institute For ASIC Training STA & Timing Paths
Synthesis Constraints
SoC Design Training Institute Design Partition
Institute For ASIC Training HDL Coding Guidelines

Design For Test

Fault Models
SoC Design Training Institute ATPG Algorithms
Institute For ASIC Training At-Speed Testing
IDDQ Test & Memory BIST
SoC Design Training Institute I/O Testing
Institute For ASIC Training Pattern Generation

 

Institute of ASIC Training
 

ASIC Physical Design Flow

Place & Route

Floor Planning
SoC Design Training Institute I/O Ring and Power Grid Planning
Institute For ASIC Training Placement Methodologies
Clock Tree Synthesis
SoC Design Training Institute Routing & Timing Optimization
Institute For ASIC Training Parasitic Extraction

Physical Verification

Testbench Modifications for GLS
SoC Design Training Institute Static Timing Analysis
Institute For ASIC Training DRC LVS ERC

Institute of VLSI Training
   

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