VLSI Training Banagalore

VLSI Training in Bangalore

Detailed Syllabus - IIVDT ADVDT

Advanced Diploma in VLSI Design Technology is an intensive and highly modular course with each module provides comprehensive training on specific aspect of the VLSI Design flow. Each module contains thorough case study or tutorial to convert knowledge into learning. After each module students have to appear and clear online test to continue further in the stream.

Beside the tutorials and online examinations, student's learning is also evaluated through group project taken during the course. Due to world class course content and rigorous evaluation criterions, ADVDT lifts the knowledge of the students in VLSI Design domain to the professional level. This proficiency in VLSI Design flow enables students to get easily absorbed in VLSI industry.

Below is the detailed Syllabus for Advanced Diploma in VLSI Design Technology

SoC Design Training India

Front End VLSI Design Training Flow

Architecture

	SoC Bus Structure - AHB, APB, AXI
	SoC Processor Architecture
	SoC Peripherals

	Area Optimization
	Frequency Optimization
	SoC Architecture Tutorial

Logic Design

	FSM Design & FIFO Design
	Verilog Coding
	Handshaking Protocols

	Math Function Implementations
	Reset Design
	Clock Management

Advanced Verification

	Testbench Architecture
	System Verilog & Assertions
	Verification Methodologies

	Coverage Methods
	GLS Verification & Debugging Tips
	Verification Tutorial

ASIC Design Training

ASIC Netlist Generation Flow

RTL Synthesis

	Synthesis Strategies
	Synthesis Scripts
	STA & Timing Paths

	Synthesis Constraints
	Design Partition
	HDL Coding Guidelines

Design For Test

	Fault Models
	ATPG Algorithms
	At-Speed Testing

	IDDQ Test & Memory BIST
	I/O Testing
	Pattern Generation

Institute of ASIC Training

ASIC Physical Design Flow

Place & Route

	Floor Planning
	I/O Ring and Power Grid Planning
	Placement Methodologies

	Clock Tree Synthesis
	Routing & Timing Optimization
	Parasitic Extraction

Physical Verification

	Testbench Modifications for GLS
	Static Timing Analysis
	DRC LVS ERC

Institute of VLSI Training

VLSI Industry Process & Soft Skills

Processess

	Version Control Process
	Review Process
	Tape-out Checklist Process

	RTL Release Process
	Bug Tracking Methodologies

Documentation

	Architecture Document
	Design Document
	Verification Plan

	DFT Plan
	Synthesis & P 'n' R Plan

Soft Skills

	Personal Etiquettes
	Resume Tips
	Technical Round Interview Tips

	HR Round Interview Tips
	Mock Interviews